There are a number of applications in which it is desirable to recover data in an asynchronous data stream. As used herein, the term “asynchronous” implies that the regular events in the data stream are not synchronous to a “system” or master clock in a device, but the data is assumed to contain an average or dominant frequency.
A phase-locked loop (“PLL”) is a well-known circuit used to generate a local data clock or “recovered clock” that is synchronous to the input data stream by locking onto the average or dominant frequency present in the input stream. The PLL typically has a phase detector, a filter, and a voltage-controlled oscillator (“VCO”) that generates the “recovered clock” signal by locking on to the average or dominant frequency of the input stream. This allows the PLL to gather the data from the input stream, using, for example, a D-type flip-flop (“DFF”) as shown in FIG. 1.
However, a device or system typically has a system or master clock, and the “recovered clock” generated by the PLL method of recovery of data generally does not have the same frequency as the master clock. Thus, data received from the input stream must be further processed to ensure that the system and the recovered data from the input stream remain in step with each other.
In addition, there are a number of issues around both VCOs and phase detectors. Both VCOs and certain types of phase detectors suffer from jitter, which may be perceptible as a degradation of the recovered data from the input signal. Some types of phase detectors may suffer from a “false lock” condition in which the PLL synchronizes with the wrong phase of the input signal or with the wrong frequency (e.g., a harmonic of the input signal), while other types of phase detectors suffer from a “dead band” (in which the phases of inputs are close enough that the detector fires on either both or neither of the appropriate charge pulses). (While the filter is also important for smoothing the output of the phase detector, those of skill in the art will easily be able to select an appropriate filter.)
As a result of these issues, those of skill in the art will appreciate the various, often complicated, design considerations that must go into the implementation of a PLL.
For these and other reasons, it is desirable to have a way of recovering asynchronous data at the frequency of the input data stream while using a single clock, and without analog components such as phase detectors or VCOs.